1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method for fabricating a capacitor of a semiconductor device in which its process is simplified and capacitance is efficiently improved.
2. Discussion of the Related Art
Miniaturization and integrity density of electrical circuits are realized due to development of fabricating technology of semiconductor devices. For example, mass production of 16M DRAMs (dynamic random access memories) and 64M DRAMs has been proceeded. Moreover, research and development is being directed to DRAMs with a higher integrity density.
As integrity densities of devices increase, areas for capacitors of cells drastically decrease. Thus, the major issues to improve integrity density of DRAMs are capacitor-fabricating technologies capable for realizing capacitors with equivalent capacitance even in reduced areas of capacitors.
A conventional method for fabricating a capacitor of a semiconductor device will be described with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view showing a structure of a conventional capacitor.
High dielectric constant materials, i.e., BaSrTiO.sub.3 (BST), BaTiO.sub.3, PbZrTiO.sub.3 (PZT), and PbZrO.sub.3 have been strongly proposed in fabricating methods of capacitors.
A conventional capacitor for which high dielectric constant material is used includes a well 2 formed in a semiconductor substrate 1; device-isolating layers 3 formed on the well 2; a gate electrode 5a, 5b, and 5c formed on a channel region in each of active regions isolated by device-isolating layers 3; impurity diffusion regions 4 used as source and drain regions formed by an impurity ion-implanting process with the gate electrode 5a, 5b, and 5c serving as a mask; a first interlayer insulating layer 6 formed on the entire surface of the semiconductor substrate 1 to have a contact hole; a bit line 7 consisting of a polysilicon plug layer 7a and a silicide layer 7b formed on the polysilicon plug layer 7a, wherein the polysilicon plug layer contacts with the impurity diffusion region 4 at one side of the gate electrode 5a, 5b, and 5c through the contract hole of the first interlayer insulating layer 6; a second interlayer insulating layer 8 formed on the entire surface including the bit line 7; a lower electrode layer 9 consisting of a polysilicon plug layer 9a, a barrier layer 9b formed on the polysilicon plug layer 9a, and a metal electrode layer 9c formed on the barrier layer 9b, wherein the polysilicon plug layer 9a contacts with the impurity diffusion region 4 at the other side of the gate electrode 5a, 5b, and 5c through the contact hole of the first and second interlayer insulating layers 6 and 8.
High dielectric constant films are used to heighten capacitance in the above-described capacitor of a semiconductor device. However, the capacitor has the following problems.
First, a silicon oxide film is formed at interface of a polysilicon electrode and a high dielectric constant film in case that a polysilicon layer is used as an electrode of a capacitor, thereby deteriorating device performances.
Second, since a deposition temperature of a high dielectric constant film is about 600-700.degree. C., a material for electrodes should have a high melting point and oxidation resistance. In other words, the range of materials used as electrodes is limited. There should be used only materials such as Pt, Pd, Rh, RuO, IrO.sub.2 which are not oxidized. Accordingly, improvement of electrode structure and development of its process should be accomplished in order to use a high dielectric constant material for a capacitor.
In the typical structure of a conventional electrode, there is formed a contact plug layer made of polysilicon, upon which there is formed a metal electrode made of Pt that has a good conductivity and is not oxidized. In this case, since there exists an interface of the contact plug layer and the metal electrode, a considerable amount of silicide nuclear is generated by reaction of the metal and the silicon. Besides, due to annealing process after depositions of a dielectric film of a capacitor, an insulating layer for wiring, and so forth, they are easily converted to silicide. This reaction of conversion into silicide causes changes in volume of the lower electrode, thereby generating void, crack, and stress. Silicide is characterized in being easily oxidized so that the entire metal lower electrtode becomes thin. In order to solve this problem, barrier metal layer against oxidation or reaction has been used.
However, formation of such barrier metal layers increase production cost and make the process complex. Further, mutual diffusion of elements at the interface can not be controlled completely.